Download slides from our October 25, 2011 webinar “Solving Next-Generation Intel Architecture Design Challenges – Signal Integrity, Power Distribution, and Thermal”
The convergence of new high-speed processor interconnects and network interfaces with ever higher levels of circuit density, memory speed, and integration results in a rapidly growing set of design challenges awaiting developers of next-generation IA (Intel Architecture or x86) products. With intense time to market pressures, developers cannot afford to let these challenges impact their programs.
Read more below and download slides from our October 25, 2011 webinar to learn how to tame the challenges of signal integrity on high-speed interfaces (DDR3, QPI, PCIe Gen2/3, 10-40Gb Ethernet), power distribution, and thermal design facing developers of latest generation embedded x86 systems.
Advanced x86 Design Articles
PCI-SIG Presentation: PCIe 2.0 Signal Integrity Considerations
In this very informative presentation to the PCI-SIG, Jeff Loyer discusses how the “fiberweave effect” can impair PCI Express Gen 2 links, along with printed circuit board design and fabrication techniques to mitigate the problems.
eLearning Technical Library: SiSoft Signal Integrity Design and Simulation Tutorials
SiSoft, Inc. is a leading provider of signal integrity design and simulation tools and component models. In this extensive technical library, SiSoft has posted more than 50 eLearning papers and presentations that cover a broad range of topics in state of the art design for signal integrity.
Video: Intel Signal Integrity How-To Tutorial
In this tutorial video, Intel signal integrity engineer Vira Ragavassamy discusses how to design for signal integrity with Intel processors, and the specific steps that can help developers reach high confidence results faster.